1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, and more specifically a method for forming a wiring conductor in a semiconductor device including an N.sup.+ diffused layer and a P.sup.+ diffused layer, such as a semiconductor device including CMOS transistors.
2. Description of Related Art
With microminiaturization of semiconductor devices, the depth of a junction of an N.sup.+ diffused layer and a P.sup.+ diffused layer has become shallow in a semiconductor device including CMOS (complementary MOS (metal-oxide-semiconductor field effect transistor)) transistors. In this structure, a contact hole is formed to pass through an insulator film covering the N.sup.+ diffused layer and the P.sup.+ diffused layer, and a wiring conductor is formed to be connected through the contact hole to the N.sup.+ diffused layer or the P.sup.+ diffused layer. However, the wiring conductor is apt to break a junction of the N.sup.+ diffused layer or the P.sup.+ diffused layer. In order to avoid this problem, N type ions and P type ions are implanted at a bottom of the contact hole reaching the N.sup.+ diffused layer and the P.sup.+ diffused layer (this is called a "contact ion implantation"), and then, a heat treatment is performed to deepen the junction in these portions. In this contact ion implantation, however, the insulator film (and an insulative photoresist film) is electrified with a large amount of electric charges, with the result that an electrostatic destruction is apt to occur for these electric charges.
Japanese Patent Application Laid-open Publication JP-A-1-186668 proposes one semiconductor device manufacturing method capable of preventing the electrostatic destruction caused by the contact ion implantation. The disclosure of JP-A-1-186668 is incorporated by reference in its entirety into the present application. Referring to FIGS. 1A to 1D, there are shown diagrammatic sectional views illustrating this proposed method for manufacturing a semiconductor device, which is as follows:
An N-well 202 is formed in a predetermined region of a surface of a P-type silicon substrate 201 as shown in FIG. 1A. Then, a field oxide film, a gate oxide film and a gate electrode are formed, but are not shown in the drawing for avoiding complication of the drawing. Furthermore, an N.sup.+ diffused layer 203 is formed in another predetermined region of the surface of the P-type silicon substrate 201 where the N-well 202 is not formed, and a P.sup.+ diffused layer 204 is formed in a predetermined region of a surface of the N-well 202. An insulator film 205 is formed to cover the surface of P-type silicon substrate 201 including the surface of the N-well 202, and a refractory metal film 207 is further formed to cover the insulator film 205. Thereafter, the refractory metal film 207 and the insulator film 205 are selectively and sequentially etched by using a patterned photoresist (not shown) as a mask, so as to form a contact hole 206A reaching the N.sup.+ diffused layer 203 and a contact hole 206B reaching the P.sup.+ diffused layer 204.
Succeedingly, the patterned photoresist (not shown) is removed, another photoresist 209A covering the contact hole 206B but having an opening in alignment with the contact hole 206A, is formed. A contact ion implantation is performed with a high dose of N-type impurities by using the photoresist 209A (and the insulator film 205) as a mask. Thus, an ion-implanted N-type region 213 is formed in the surface of the N.sup.+ diffused layer 203 at a bottom of the contact hole 206A, as shown in FIG. 1A.
Furthermore, the photoresist 209A is removed, still another photoresist 209B covering the contact hole 206A but having an opening in alignment with the contact hole 206B, is formed. Another contact ion implantation is performed with a high dose of P-type impurities by using the photoresist 209B (and the insulator film 205) as a mask. Thus, an ion-implanted P-type region 214 is formed in the surface of the P.sup.+ diffused layer 204 at a bottom of the contact hole 206B, as shown in FIG. 1B.
Thereafter, the photoresist film 209B is removed, and a heat treatment is carried out, so that the ion-implanted N-type region 213 and the ion-implanted P-type region 214 are diffused to form an N.sup.+ diffused region 223 and a P.sup.+ diffused region 224, as shown in FIG. 1C. The N.sup.+ diffused region 223 becomes deeper than the N.sup.+ diffused layer 203, and the P.sup.+ diffused region 224 becomes deeper than the P.sup.+ diffused layer 204.
The aluminum film is deposited to cover a whole surface, and the stacked layer composed of the aluminum film and the refractory metal film 207 are patterned to form wiring conductors 211A and 211B, as shown in FIG. 1D. The wiring conductor 211A is electrically connected through the contact hole 206A to (the N.sup.+ diffused region 223 and) the N.sup.+ diffused layer 203. This wiring conductor 211A is composed of only aluminum 210A within the contact hole 206A, but of the stacked layer composed of the aluminum film 210A and the refractory metal film 207A, in an area other than the contact hole 206A. Similarly, the wiring conductor 211B is electrically connected through the contact hole 206B to (the P.sup.+ diffused region 224 and) the P.sup.+ diffused layer 204. This wiring conductor 211B is composed of only aluminum 210B within the contact hole 206B, but of the stacked layer composed of the aluminum film 210B and the refractory metal film 207B, in an area other than the contact hole 206B.
In the above mentioned conventional manufacturing method, JP-A-1-186668 gives such an explanation that, since the refractory metal film 207 exists under the photoresist film 209A in the process for the contact ion implantation, for example when the ion-implanted N-type region 213 is formed, the electrostatic destruction caused by the accumulated electric charges does not occur. However, although an upper edge of the contact hole 206A is covered with the refractory metal film 207, a side surface of the contact hole 206A is defined by the insulator film 205, and therefore, the refractory metal film 207 is not electrically connected to the N.sup.+ diffused layer 203. Similarly, the refractory metal film 207 is not electrically connected to the P.sup.+ diffused layer 204 in the contact hole 206B. Because of this, the electric charges accumulated on the refractory metal film 207 inevitably discharge between the refractory metal film 207 and the N.sup.+ diffused layer 203 or the P.sup.+ diffused layer 204. In other words, the method proposed by JP-A-1-186668 is not sufficiently satisfactory in preventing the electrostatic destruction caused in the process of the contact ion implantation.
Japanese Patent Application Laid-open Publication JP-A-4-101416 proposes another semiconductor device manufacturing method capable of preventing the electrostatic destruction caused by the contact ion implantation. The disclosure of JP-A-4-101416 is incorporated by reference in its entirety into the present application. Referring to FIGS. 2A to 2D, there are shown diagrammatic sectional views illustrating this proposed method for manufacturing a semiconductor device, which is as follows:
First, at a predetermined region of a surface of a semiconductor substrate 301 of a first conductivity type, a diffused layer 303 of a second conductivity type opposite to the first conductivity type is formed, and an insulator film 305 is formed to cover the whole surface. Then, a contact hole 306 is formed to pass through the insulator film 305 to reach the diffused layer 303. Furthermore, a photoresist film 309 having an opening of a size larger than that of the contact hole 306, is formed as shown in FIG. 2A.
Next, a refractory metal film 307 is deposited to cover a surface of the photoresist film 309 including an inner surface of the contact hole 306, and then, the contact ion implantation is performed by using the photoresist 309 (and the insulator film 305) as a mask, so that an ion-implanted region 313 of the second conductivity type is formed as shown in FIG. 2B.
Thereafter, the photoresist film 309 is lifted off so that a portion of the refractory metal film 307 in direct contact with the photoresist film 309 is removed, and only the refractory metal film 307A within the opening of the photoresist film 309 remains. Succeedingly, a heat treatment is performed so that the ion-implanted region 313 is activated and converted into a diffusion region 323 and the refractory metal film 307A at the bottom of the contact hole 306 is partially converted into a refractory metal silicide 317, as shown in FIG. 2C.
Furthermore, a metal film is deposited to cover the whole surface, and then, is patterned to form a wiring conductor 311. The wiring conductor 311 is formed of a stacked layer composed of the refractory metal silicide 317, the refractory metal 307A and the metal film 310 within the contact hole 306, but of a stacked layer composed of the refractory metal 307A and the metal film 310 at a periphery of the contact hole 306. In addition, at a region apart from the contact hole 306, the wiring conductor 311 is formed of only the metal film 310.
According to the semiconductor device manufacturing method of JP-A-4-101416, it is possible to prevent certainly the electrostatic destruction in the process of the contact ion implantation. Since a barrier metal film is formed at a bottom of the contact hole in the method of JP-A-4-101416, stability of the contact characteristics is more excellent than the semiconductor device manufacturing method of JP-A-1-186668. However, the method of JP-A-4-101416 can be applied to a semiconductor device including only one conductivity type of diffused layers, but when it is applied to a semiconductor device such as a CMOS semiconductor device, including two different conductivity types of diffused layers such as N-type diffused layers and P-type diffused layers, the following problems have been encountered.
First, the surface of the diffused layer at the bottom of the contact hole is contaminated. This similarly occurs in the semiconductor device manufacturing method of JP-A-1-186668. For example, in the case that the ion-implanted N-type region is formed before the P-type ion-implanted region is formed, the photoresist film (for the lift-off) is in direct contact with the surface of the P-type diffused layer at the bottom of the contact hole reaching the P-type diffused layer until the N-type ion-implanted region is formed. After the photoresist film is lifted off, the refractor metal film remains in the contact hole reaching the N-type diffused layer, and therefore, it is impossible to perform a washing by use of acid or hydrogen peroxide water. Because of this, it is not possible to remove contamination of the P-type diffused layer surface due to the photoresist film.
Secondly, the semiconductor device manufacturing method of JP-A-4-101416 is more complicated than the method of JP-A-1-186668, but is lower than the method of JP-A-1-186668 in a workability of the wiring conductor and in an anti-stress-migration property of the wiring conductor. For example, according to the semiconductor device manufacturing method of JP-A-1-186668, the wiring conductor has a uniform structure in an area other than the contact hole, but according to the semiconductor device manufacturing method of JP-A-4-101416, the wiring conductor includes a single layer or two layers of the refractory metal film in one area but does not include a refractory metal film in another area. This adversely affects the workability of the wiring conductor and lowers the anti-stress-migration property of the wiring conductor.